1. Field of the Invention
The present invention relates to circuit configuration of a static RAM (SRAM). More specifically, the invention relates to a technique suppressing occurrence of leak current in the SRAM.
2. Related Background Art
A static RAM, which will be called a SRAM hereafter, is generally utilized to a cache memory inside a CPU and so on, because the SRAM is not in need of performing refreshing and is enable to access for memory cell with high speed.
FIG. 13 is a circuit showing an internal configuration of a conventional MOS type of the SPAM. The circuit shows the configuration per one column. The SRAM in FIG. 13 includes bit lines BL, /BL and word lines W, which are arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 provided for pre-charge, MOS transistors Q3 provided for short-circuiting, and MOS transistors Q4 and Q5 provided for setting voltage level of a pair of bit lines BL and /BL.
The transistors Q1 and Q2 controls so that the pair of the bit lines become high level just before reading out of the memory cell 1 and writing in the memory cell 1. The transistor Q3 controls so that the pair of bit lines becomes the same voltage.
Inside the SRAM in FIG. 13, two pieces of the bit lines is provided at each bit. These bit lines are set to contrary logic to each other, in case of reading out of the memory cell 1 and writing in the memory cell 1.
In case of forming the SRAM shown in FIG. 13 on the semiconductor substrate, it is general to form the bit lines BL and /BL by using AL layer with lower impedance. However, due to the progress of minute process technique, memory capacity of the SRAM is tend to increase by degrees, while the width of wires and the space between the wires become short. Accordingly, the defect due to the leak current and so on is prone to occur.
More especially, in case of being integrated highly, because it becomes inevitable to arrange the bit lines BL and /BL, the word lines W and so on adjacently to each other, as shown in FIG. 13, cases which cannot but arrange the ground lines Vss beside the bit lines BL and /BL increase.
However, when the bit lines BL and /BL and the ground lines Vss are arranged adjacently, all of the lines BL, /BL and Vss are prone to short-circuit to each other. If short-circuited, the leak current flows from the bit lines driving power supply terminal Vcc to the ground line Vss via the bit lines BL and /BL.
As shown in FIG. 14, the bit lines BL and the drain terminal 11 of transfer gates in the memory cell 1 are connected to each other via the contact hole 12. Accordingly, when the width of the bit lines is thin, if the hole position of the contact hole 12 deviates barely, the bit lines BL contacts with the ground line Vss, and the leak current flows from the power supply terminal Vcc to the ground line Vss via the contact hole 12; consequently, it becomes impossible to fill the spec of a current at a static operating period. Such a state is called "standby defect" hereafter.
Among the conventional SRAM, there are ones including a redundancy circuit which replaces the defective memory cell unable to correctly read out and write in, the defect being called a function defect hereafter, by the other memory cell. However, even if the defective memory cell is replaced by the redundancy circuit, it is impossible to reduce the leak current. Accordingly, with only the replacement of the memory cell occurring the leak, though it is possible to relieve the function defect, it is impossible to relieve the standby defect.
As a way to suppress the leak current of the bit lines, a SRAM which cuts a route that the leak current has occurred has been proposed. FIG. 15 is a diagram showing internal configuration of such a kind of SRAM, which is disclosed to Japanese publication of publication number H5-314790. The SRAM in FIG. 15 has a feature in which a PMOS transistor 22 and a fuse 23 are provided between a memory cell 21 and a power supply terminal. A memory cell is composed of a circuit similar to one shown in FIG. 16A or FIG. 16B.
The circuit in FIG. 15 includes a fuse 23 connected between the power supply terminal Vcc and the drain terminal of MOS transistors 24 and 25 in the memory cell 21. However, even if the fuse is cut, the leak current flowing through the bit lines is not suppressed.
FIG. 16A shows an example that a memory cell is composed of four MOS transistors, and FIG. 16B shows an example that a memory cell is composed of two MOS transistors and two resistors with high resistance. The circuit in FIG. 16B is enable to reduce the cell area.
On the other hand, Japanese publication of publication number H8-138399 discloses a circuit cutting the power supply line by means of the MOS transistor when the leak defect has occurred. In this publication, as shown in FIG. 17, an example providing fuses in a power supply control circuit which controls a gate voltage is being disclosed. However, in the circuit in FIG. 17, even if the fuse is cut, the power supply line is not cut. Accordingly, the circuit is complicated, and element forming area and power consumption are prone to increase.
Instead of the MOS transistor showing in FIG. 17, it is also possible to provide the fuse with simpler configuration than the MOS transistor. It is general to form the fuse out of polysilicon, the resistance being higher than the bit lines formed out of aluminum or the like. Accordingly, in case of connecting the fuse between the power supply terminal Vcc and the bit lines, the voltage drop occurs at both ends of the fuse, and the voltage supplied to the bit lines declines. In order to supplement this voltage drop, it is conceivable to heighten the voltage applied to the power supply terminal Vcc. However, in this case, it becomes impossible to drive with a low voltage; consequently, the power consumption increases.
FIG. 18 is a layout diagram of the conventional semiconductor memory device including a redundancy circuit. The semiconductor memory device in FIG. 18 is divided into four blocks B1-B4. A redundancy circuit RD1 in the column direction and a redundancy circuit RD2 in the row direction are provided inside each of the blocks B1-B4. In the column direction, a plurality of section regions SEC0-SEC7 are provided at each column address. The replacement by the redundancy circuit RD1 is performed at each of the section regions SEC0-SEC7
FIG. 19 is an enlarged diagram showing one block in FIG. 18. A part enclosed with a dotted line in FIG. 19 corresponds to each of the section regions SEC0-SEC7. Between two section regions adjacent to each other, a word line drive circuit WSL is provided. A cell ground power supply line Vss is provided inside each of the section regions SEC0-SEC7. These cell ground power supply line Vss is connected to a pad grounded power supply line Vss' formed outside each of the section regions SEC0-SEC7.
Sense amplifiers S/A0-S/A7 amplifying a signal read out from the memory cell 1 are connected to one ends of the section regions SEC0-SEC7, respectively. These sense amplifiers S/A0-S/A7 are formed at symmetric location for an axis shown by a dot-and-dashed line in FIG. 18 and FIG. 19.
According to the recent progress; of minute process technique, because the width of the wires and the space between the wires also become short, the defect which the signal lines of the bit lines and so on, and the ground line Vss short-circuit, that is, "standby defect", is prone to occur. When such a kind of standby defection occurs, the penetrating current flows from the power supply line Vcc to the ground line Vss; consequently, the power consumption of the semiconductor memory device increases.
Though the redundancy circuits RD1 and RD2 showing in FIG. 18 and FIG. 19 can relieve the function defect, it is impossible to relieve the standby defect. Even if the memory cell that the standby defect has occurred is replaced by the redundancy circuits RD1 or RD2, the leak current flows; consequently, it is impossible to improve production yield.